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ds05-20890-1e fujitsu semiconductor data sheet page mode flash memory cmos 32 m (2 m 16/1 m 32) bit mbm29pl3200te/be 70/90 n n n n description the mbm29pl3200te/be is 32 m-bit, 3.0 v-only page mode flash memory organized as 2 m words of 16 bits each or 1 m words of 32 bits each. the device is offered in 90-pin ssop and 84-ball fbga packages. this device is designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the device can also be reprogrammed in standard eprom pro- grammers. (continued) n n n n product line-up n n n n packages part no. mbm29pl3200te/be ordering part no. v cc = 3.3 v 70 ? v cc = 3.0 v ? 90 max. random address access time (ns) 70 90 max. page address access time (ns) 25 35 max. ce access time (ns) 70 90 max. oe access time (ns) 25 35 + 0.3 v - 0.3 v + 0.6 v - 0.3 v 90-pin plastic ssop 84-ball plastic fbga (fpt-90p-m01) (bga-84p-m01)
mbm29pl3200te/be 70/90 2 (continued) the device provides truly high performance non-volatile flash memory solution. the device offers fast page access times of 25 ns and 35 ns with random access times of 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the device has separate chip enable (ce ), write enable (we ) and output enable (oe ) controls. the page size is 8 words or 4 double words. the device is command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state- machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the device is programmed by executing the program command sequence. this will invoke the embedded program tm * algorithm, which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. typically, each sector can be programmed and verified in about 2.2 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase tm * algorithm, which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margins. any individual sector is typically erased and verified in 4.8 second. (if already preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the device is erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , output pin. once the end of a program or erase cycle has been completed, the device internally resets to the read mode. fujitsus flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the device memory electrically erases all bits within a sector simultaneously via fowler-nordhiem tunneling. the words/double words are programmed one word/double word at a time using the eprom programming mechanism of hot electron injection. *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc. n n n n features ? 0.23 m m m m m process technology ? single 3.0 v read, program and erase minimized system level power requirements ? high performance page mode 25 ns maximum page access time (70 ns random access time) ? 8 words page ( 16) /4 double words ( 32) size ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts 90-pin ssop (package suffix : pfv) 84-ball fbga (package suffix : pbt) ? minimum 100,000 program/erase cycles ? sector erase architecture one 16 k word, two 8 k words, one 96 k word, and fifteen 128 k words sectors in word mode ( 16) one 8 k double word, two 4 k double words, one 48 k double word, and fifteen 64 k double words sectors in double word mode ( 32) any combination of sectors can be concurrently erased. also supports full chip erase
mbm29pl3200te/be 70/90 3 ? boot code sector architecture t = top sector b = bottom sector ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm algorithms automatically programs and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switches themselves to low power mode ? low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector protection hardware method disables any combination of sectors from program or erase operations ? fast programming function by extended command ? temporary sector unprotection temporary sector unprotection with the software command ? in accordance with cfi (c ommon f lash memory i nterface)
mbm29pl3200te/be 70/90 4 n n n n pin assignments (continued) ssop (top view) fpt-90p-m01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 n.c. n.c. acc wp we n.c. n.c. n.c. dw/w oe ce v ss dq 31 /a -1 dq 15 dq 30 dq 14 v ss v cc dq 29 dq 13 dq 28 dq 12 dq 27 dq 11 dq 26 dq 10 v ss v cc dq 25 dq 9 dq 24 dq 8 v cc a 19 a 18 a 17 a 16 a 15 a 14 a 13 n.c. n.c. n.c. n.c. n.c. 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 n.c. n.c. n.c. n.c. n.c. a 0 a 1 a 2 a 3 a 4 a 5 v cc dq 0 dq 16 dq 1 dq 17 v ss v cc dq 2 dq 18 dq 3 dq 19 dq 4 dq 20 dq 5 dq 21 v ss v cc dq 6 dq 22 dq 7 dq 23 v ss a 6 a 7 a 8 a 9 a 10 a 11 a 12 n.c. n.c. n.c. n.c. n.c.
mbm29pl3200te/be 70/90 5 (continued) fbga (top view) marking side bga-84p-m01 b9 dq 30 c9 v cc d9 dq 13 e9 dq 12 f9 dq 27 g9 dq 26 h9 v cc j9 dq 9 a8 b8 j8 h8 g8 f8 e8 d8 c8 k8 ce v ss v cc dq 24 v ss dq 11 dq 28 dq 29 dq 15 a 19 a7 b7 j7 h7 g7 f7 e7 d7 c7 k7 n.c. dw/w a 17 a 18 dq 25 dq 10 v ss dq 14 oe a 16 a6 b6 j6 h6 g6 f6 e6 d6 c6 k6 we n.c. a 14 a 15 dq 8 n.c. n.c. dq 31 /a -1 n.c. a 13 a5 b5 j5 h5 g5 f5 e5 d5 c5 k5 n.c. acc n.c. n.c. n.c. n.c. n.c. n.c. wp n.c. a4 b4 j4 h4 g4 f4 e4 d4 c4 k4 a 1 a 2 a 9 a 11 a 12 n.c. dq 2 a 0 a 3 a 10 a3 b3 j3 h3 g3 f3 e3 d3 c3 k3 a 4 a 5 a 6 a 8 dq 21 dq 5 dq 18 dq 16 dq 0 a 7 b2 j2 h2 g2 f2 e2 d2 c2 k2 v cc dq 23 dq 7 dq 6 dq 4 dq 19 v ss dq 1 v ss j1 h1 g1 f1 e1 d1 c1 dq 22 v cc v ss dq 20 dq 3 v cc dq 17
mbm29pl3200te/be 70/90 6 n n n n pin descriptions table 1 mbm29pl3200te/be pin configuration n n n n block diagram pin name function a 19 to a 0 , a -1 address input dq 31 to dq 0 data input/output ce chip enable oe output enable we write enable dw/w selects 32-bit or 16-bit mode wp hardware write protection acc program acceleration n.c. pin not connected internally v ss device ground v cc device power supply a 1 , a 0 (a - 1 ) v ss v cc we ce a 19 to a 29 oe dq 31 to dq 0 dw/w wp acc stb stb erase voltage generator state control circuit (command register) program voltage generator input/output buffers data latch chip enable output enable logic low v cc detector timer for program/erase address latch y-decoder x-decoder y-gating 33,554,432 cell matrix
mbm29pl3200te/be 70/90 7 n n n n logic symbol 20 a 19 to a 0 we oe ce dq 31 to dq 0 32 or 16 dw/w a -1
mbm29pl3200te/be 70/90 8 n n n n device bus operation table 2 mbm29pl3200te / be user bus operations ( dw / w = v ih ) legend : l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see table 4. *2: refer to section on sector protection. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 3.3 v 10 % *5: protect outermost 16 k words (8 k double words) of the boot block sectors. table 3 mbm29pl3200te / be user bus operations ( dw / w = v il ) legend : l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see table 4. *2: refer to section on sector protection. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 3.3 v 10 % *5: protect outermost 16 k words (8 k double words) of the boot block sectors. operation ce oe we a 0 a 1 a 2 a 3 a 6 a 9 dq 31 to dq 0 wp auto-select manufacturer code * 1 llhlllllv id code x auto-select device code * 1 llhhllllv id code x extended auto-select device code * 1 l lhhhhhlv id code x read * 3 llha 0 a 1 a 2 a 3 a 6 a 9 d out x standby h x x xxxxxx high-z x output disable lhhxxxxxx high-z x write (program/erase) l h l a 0 a 1 a 2 a 3 a 6 a 9 d in x enable sector protection * 2, * 4 lv id lhlllv id xx verify sector protection * 2, * 4 llhlhlllv id code x boot block sector write protection * 5 xxxxxxxxx x l operation ce oe we dq 31 /a- 1 a 0 a 1 a 2 a 3 a 6 a 9 dq 15 to dq 0 wp auto-select manufacturer code * 1 ll h l lllllv id code x auto-select device code * 1 ll h l hllllv id code x extended auto-select device code * 1 l l h l hhhhlv id code x read * 3 ll h a- 1 a 0 a 1 a 2 a 3 a 6 a 9 d out x standby h x x x xxxxxx high-z x output disable lh h x xxxxxx high-z x write (program/erase) l h l a- 1 a 0 a 1 a 2 a 3 a 6 a 9 d in x enable sector protection * 2, * 4 lv id l lhlllv id xx verify sector protection * 2, * 4 ll h l lhlllv id code x boot block sector write protection * 5 xx x x xxxxxx x l
mbm29pl3200te/be 70/90 9 table 4 mbm29pl3200te / be command definitions (continued) command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset dw 1xxxhf0h ?????????? w read/reset dw 3 555h aah 2aah 55h 555h f0h ra rd ???? w aaah 555h aaah autoselect dw 3 555h aah 2aah 55h 555h 90h ?????? w aaah 555h aaah program dw 4 555h aah 2aah 55h 555h a0h pa pd ???? w aaah 555h aaah chip erase dw 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h w aaah 555h aaah aaah 555h aaah sector erase dw 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h w aaah 555h aaah aaah 555h erase suspend 1 xxxh b0h ?????????? erase resume 1 xxxh 30h ?????????? set to fast mode dw 3 555h aah 2aah 55h 555h 20h ?????? w aaah 555h aaah fast program * 1 dw 2 xxxh a0h pa pd ???????? wxxxh reset from fast mode * 1 dw 2 xxxh 90h xxxh * 4 f0h ???????? w xxxh xxxh temporary unprotection enable dw 4 555h aah 2aah 55h 555h e0h xxxh 01h ???? w aaah 555h aaah temporary unprotection disable dw 4 555h aah 2aah 55h 555h e0h xxxh 00h ???? w aaah 555h aaah query * 2 dw 1 55h 98h ? ????????? waah hi-rom entry dw 3 555h aah 2aah 55h 555h 88h ?????? w aaah 555h aaah hi-rom program * 3 dw 4 555h aah 2aah 55h 555h a0h (hra) pa pd ???? w aaah 555h aaah hi-rom exit * 3 dw 4 555h aah 2aah 55h 555h 90h xxxh 00h ???? w aaah 555h aaah
mbm29pl3200te/be 70/90 10 (continued) dw : double word w : word *1: this command is valid while fast mode. *2: the valid addresses are a 6 to a 0 . *3: this command is valid while hi-rom mode. *4: the data 00h is also acceptable. notes : 1.address bits a 19 to a 11 = x = h or l for all address commands except or program address (pa), and sector address (sa). 2.bus operations are defined in tables 2 and 3. 3.ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 will uniquely select any sector. 4.rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the falling edge of write pulse. 5.hra = address of the hi-rom area word mode : 000000h to 000100h double word mode : 000000h to 000080h 6.the system should generate the following address patterns : dw (double word) mode : 555h or 2aah to addresses a 10 to a 0 w (word) mode : aaah or 555h to addresses a 10 to a 0 , and a- 1 7.both read/reset commands are functionally equivalent, resetting the device to the read mode.
mbm29pl3200te/be 70/90 11 table 5.1 mbm29pl3200te sector protection verify autoselect codes *1 : a- 1 is for word mode. in double word mode, dq 15 to dq 30 become high-z and dq 31 becomes the lower address a- 1 . *2 : outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. *3 : outputs 01h at temporary sector unprotection and outputs 00h at non temporary sector unprotection. type a 19 to a 12 a 6 a 3 a 2 a 1 a 0 a- 1 * 1 code (hex) manufactures code x v il v il v il v il v il v il 04h device code word xv il v il v il v il v ih v il 227eh double word x 2222227eh extended device code word xv il v ih v ih v ih v il v il 2203h double word x 22222203h word xv il v ih v ih v ih v ih v il 2201h double word x 22222201h sector protection sector addresses v il v il v il v ih v il v il 01h * 2 temporary sector unprotection xv il v il v il v ih v ih v il 01h * 3
mbm29pl3200te/be 70/90 12 table 5.2 expanded autoselect code (w) : word mode (dw) : double word mode type code dq 31 dq 30 dq 29 dq 28 dq 27 dq 26 dq 25 dq 24 dq 23 dq 22 dq 21 dq 20 dq 19 dq 18 dq 17 dq 16 manufacturers code 04h a- 1 /0 000000000000000 device code (w) 227eh a- 1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z (dw) 2222 227eh 0010001000100010 extended device code (w) 2203h a- 1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z (dw) 2222 2203h 0010001000100010 (w) 2201h a- 1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z (dw) 2222 2201h 0010001000100010 sector protection 01h a- 1 /0 000000000000000 temporary sector unprotection 01h a- 1 /0 000000000000000 type dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code0000000000000100 device code (w)0010001001111110 (dw)0010001001111110 extended device code (w)0010001000000011 (dw)0010001000000011 (w)0010001000000001 (dw)0010001000000001 sector protection 0000000000000001 temporary sector unprotection 0000000000000001
mbm29pl3200te/be 70/90 13 table 5.3 mbm29pl3200be sector protection verify autoselect codes *1 : a- 1 is for word mode. in double word mode, dq 15 to dq 30 become high-z and dq 31 becomes the lower address a- 1 . *2 : outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. *3 : outputs 01h at temporary sector unprotection and outputs 00h at non temporary sector unprotection. type a 19 to a 12 a 6 a 3 a 2 a 1 a 0 a- 1 * 1 code (hex) manufactures code x v il v il v il v il v il v il 04h device code word xv il v il v il v il v ih v il 227eh double word x 2222227eh extended device code word xv il v ih v ih v ih v il v il 2203h double word x 22222203h word xv il v ih v ih v ih v ih v il 2200h double word x 22222200h sector protection sector addresses v il v il v il v ih v il v il 01h * 2 temporary sector unprotection xv il v il v il v ih v ih v il 01h * 3
mbm29pl3200te/be 70/90 14 table 5.4 expanded autoselect code (w) : word mode (dw) : double word mode type code dq 31 dq 30 dq 29 dq 28 dq 27 dq 26 dq 25 dq 24 dq 23 dq 22 dq 21 dq 20 dq 19 dq 18 dq 17 dq 16 manufacturers code 04h a- 1 /0 000000000000000 device code (w) 227eh a- 1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z (dw) 2222 227eh 0010001000100010 extended device code (w) 2203h a- 1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z (dw) 2222 2203h 0010001000100010 (w) 2200h a- 1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z (dw) 2222 2200h 0010001000100010 sector protection 01h a- 1 /0 000000000000000 temporary sector unprotection 01h a- 1 /0 000000000000000 type dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 0000000000000100 device code (w)0010001001111110 (dw)0010001001111110 extended device code (w)0010001000000011 (dw)0010001000000011 (w)0010001000000000 (dw)0010001000000000 sector protection 0000000000000001 temporary sector unprotection 0000000000000001
mbm29pl3200te/be 70/90 15 table 7 sector address (mbm29pl3200te) note : the address range is a 19 to a -1 if in word mode (dw/w = v il ). the address range is a 19 to a 0 if in double word mode (dw/w = v ih ). sector sector address sector size (kwords/ double kwords) ( 16) address range ( 32) address range a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sa0 0 0 0 0 x x x x 128/64 000000h to 01ffffh 00000h to 0ffffh sa1 0 0 0 1 x x x x 128/64 020000h to 03ffffh 10000h to 1ffffh sa2 0 0 1 0 x x x x 128/64 040000h to 05ffffh 20000h to 2ffffh sa3 0 0 1 1 x x x x 128/64 060000h to 07ffffh 30000h to 3ffffh sa4 0 1 0 0 x x x x 128/64 080000h to 09ffffh 40000h to 4ffffh sa5 0 1 0 1 x x x x 128/64 0a0000h to 0bffffh 50000h to 5ffffh sa6 0 1 1 0 x x x x 128/64 0c0000h to 0dffffh 60000h to 6ffffh sa7 0 1 1 1 x x x x 128/64 0e0000h to 0fffffh 70000h to 7ffffh sa8 1 0 0 0 x x x x 128/64 100000h to 11ffffh 80000h to 8ffffh sa9 1 0 0 1 x x x x 128/64 120000h to 13ffffh 90000h to 9ffffh sa10 1 0 1 0 x x x x 128/64 140000h to 15ffffh a0000h to affffh sa11 1 0 1 1 x x x x 128/64 160000h to 17ffffh b0000h to bffffh sa12 1 1 0 0 x x x x 128/64 180000h to 19ffffh c0000h to cffffh sa13 1 1 0 1 x x x x 128/64 1a0000h to 1bffffh d0000h to dffffh sa14 1 1 1 0 x x x x 128/64 1c0000h to 1dffffh e0000h to effffh sa15 1 1 1 1 0000 to 1011 96/48 1e0000h to 1f7fffh f0000h to fbfffh sa1611111100 8/4 1f 8000h to 1f9fffh fc000h to fefffh sa1711111101 8/4 1fa000h to 1fbfffhfd 000h to fdfffh sa181111111x 16/8 1fc0 00h to 1fffffh fe000h to fffffh
mbm29pl3200te/be 70/90 16 table 8 sector address (mbm29pl3200be) note : the address range is a 19 to a -1 if in word mode (dw/w = v il ). the address range is a 19 to a 0 if in double word mode (dw/w = v ih ). sector sector address sector size (kwords/ double kwords) ( 16) address range ( 32) address range a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sa00000000x 16/8 000000h to 003fffh 00000h to 01fffh sa100000010 8/4 004000h to 005fffh 02000h to 02fffh sa200000011 8/4 006000h to 007fffh 03000h to 03fffh sa3 0 0 0 0 0100 to 1111 96/48 008000h to 01ffffh 04000h to 0ffffh sa4 0 0 0 1xxxx 128/64 020000h to 03ffffh 10000h to 1ffffh sa5 0 0 1 0xxxx 128/64 040000h to 05ffffh 20000h to 2ffffh sa6 0 0 1 1xxxx 128/64 060000h to 07ffffh 30000h to 3ffffh sa7 0 1 0 0xxxx 128/64 080000h to 09ffffh 40000h to 4ffffh sa8 0 1 0 1xxxx 128/64 0a00 00h to 0bffffh 50000h to 5ffffh sa9 0 1 1 0xxxx 128/640c00 00h to 0dffffh 60000h to 6ffffh sa100 1 1 1xxxx 128/64 0e0 000h to 0fffffh 70000h to 7ffffh sa111 0 0 0xxxx 128/64 100000h to 11ffffh 80000h to 8ffffh sa121 0 0 1xxxx 128/64 120000h to 13ffffh 90000h to 9ffffh sa131 0 1 0xxxx 128/64 140000h to 15ffffh a0000h to affffh sa141 0 1 1xxxx 128/64 160000h to 17ffffh b0000h to bffffh sa151 1 0 0xxxx 128/64 180000h to 19ffffh c0000h to cffffh sa161 1 0 1xxxx 128/64 1a00 00h to 1bffffh d0000h to dffffh sa171 1 1 0xxxx 128/641c00 00h to 1dffffh e0000h to effffh sa181 1 1 1xxxx 128/64 1e0 000h to 1fffffh f0000h to fffffh
mbm29pl3200te/be 70/90 17 table 9 common flash memory interface code (continued) a 6 to a 0 dq 15 to dq 0 description 10h 11h 12h 0051h 0052h 0059h query-unique ascii string qry 13h 14h 0002h 0000h primary oem command set 2h : amd/fj standard type 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = not applicable) 19h 1ah 0000h 0000h address for alternate oem extended table 1bh 0027h v cc min. (write/erase) d7-4 : 1 v, d3-0 : 100 mv 1ch 0036h v cc max. (write/erase) d7-4 : 1 v, d3-0 : 100 mv 1dh 0000h v pp min. voltage 1eh 0000h v pp max. voltage 1fh 0004h typical timeout per single byte/word write (2 n m s) 20h 0000h typical timeout for min. size buffer write (2 n m s) 21h 000ah typical timeout per individual block erase (2 n ms) 22h 0000h typical timeout for full chip erase (2 n ms) 23h 0005h max. timeout for byte/word write (2 n typical time) 24h 0000h max. timeout for buffer write (2 n typical time) 25h 0006h max. timeout per individual block erase (2 n typical time) 26h 0000h max. timeout for full chip erase (2 n typical time) 27h 0016h device size = 2 n byte 28h 29h 0005h 0000h flash device interface description 2ah 2bh 0000h 0000h max. number of bytes in multi-byte write = 2 n 2ch 0004h number of erase block regions within device a 6 to a 0 dq 15 to dq 0 description 2dh 2eh 2fh 30h 0000h 0000h 0080h 0000h erase block region 1 information bit0 to 15: y = number of sectors bit16 to 31: z = size (z 256 byte) 31h 32h 33h 34h 0001h 0000h 0040h 0000h erase block region 2 information bit0 to 15: y = number of sectors bit16 to 31: z = size (z 256 byte) 35h 36h 37h 38h 0000h 0000h 0000h 0003h erase block region 3 information bit0 to 15: y = number of sectors bit16 to 31: z = size (z 256 byte) 40h 41h 42h 0050h 0052h 0049h query-unique ascii string pri 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0000h address sensitive unlock 0h = required 1h = not required 46h 0002h erase suspend 0h = not supported 1h = to read only 2h = to read & write 47h 0001h sector protection 0h = not supported x = number of sectors per group 48h 0001h sector temporary unprotection 00h = not supported 01h = supported 49h 0003h sector protection algorithm 4ah 0000h 00h = not supported, x = total number of sectors in all banks except bank 1 4bh 0000h burst mode type 00h = not supported 4ch 0002h page mode type 00h = not supported
mbm29pl3200te/be 70/90 18 (continued) note : dq 31 to dq 16 = 0000h a 6 to a 0 dq 15 to dq 0 description 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-4 : 1 v, d3-0 : 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-4 : 1 v, d3-0 : 100 mv 4fh 00xxh boot type 02h = mbm29pl3200be 03h = mbm29pl3200te
mbm29pl3200te/be 70/90 19 n n n n functional description read mode the device has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for device selection. oe is the output control and should be used to gate data to the output pins when a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable prior to t acc - t oe time). when reading out data without changing addresses after power-up, it is necessary to input hardware reset or to change ce pin from h to l. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 8 words, or 4 double words, within the appropriate page being selected by the higher address bits a 19 to a 2 and the lsb bits a 1 to a 0 (in double word mode) and a 1 to a -1 (in word mode) determining the specific double word/word within that page. this is an asynchronous operation with the microprocessor supplying the specific double word or word location. the random or initial page access is equal to t acc and subsequent page read access (as long as the locations specified by the microprocessor fall within that page) is equivalent to t pa c c . here again, ce selects the device and oe is the output control and should be used to gate data to the output pins if the device is selected. fast page mode accesses are obtained by keeping a 19 to a 2 constant and changing a 1 and a 0 to select the specific double word, or changing a 1 to a -1 to select the specific word within that page. see figure 5.2 for timing speci- fications. standby mode the device has cmos standby mode (ce input held at v cc 0.3 v.), when the current consumed is less than 50 m a. in the standby mode, the output pins are in a high impedance state, independent of oe input. during embedded algorithm operation, v cc active current (i cc2 ) is required even if ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. in the standby mode, the output pins are in the high impedance state, independent of oe input. automatic sleep mode automatic sleep mode lower consumption during read-out of the device data. this mode can be useful for applications such as a handy terminal that requires low power consumption. to activate this mode, the device automatically switches itself to low power mode when addresses remain stable during access time of 150 ns. it is not necessary to control ce , we and oe in this mode. in this mode, the current consumed is typically 50 m a (cmos level). since the data are latched during this mode, they are read out continuously. if the addresses are changed, this mode is canceled automatically, and the device reads the data for changed addresses. output disable with the oe input is at a logic high level (v ih ), output from the device is disabled. this will put the output pins in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device.
mbm29pl3200te/be 70/90 20 to activate this mode, the programming equipment must force v id on address pin a 9 . three identifier words may then be sequenced from the device outputs by toggling address a 0 and a 1 from v il to v ih . all addresses are dont cares except a 6 , a 3 , a 2 , a 1 , and a 0 (a -1 ). (see tables 2 and 3.) the manufacturer and device codes may also be read via the command register, for instance when the device is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 11. (refer to autoselect command section.) a read cycle from address 00h returns the manufacturers code (fujitsu = 04h). a read cycle from address 01h, 0eh to 0fh returns the device code. (see tables 5.1 to 5.4.) in order to determine which sectors are write protected, a 1 must be at v ih while running through the sector addresses; if the selected sector is protected, a logical 1 will be output on dq 0 (dq 0 = 1). write the device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later, while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the device features hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 18). the sector protection feature is enabled using programming equipment at the users site. the device is shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , ce = v il , a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih . the sector address pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. tables 7 and 8 define the sector address for each of the nineteen (19) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see figures 15 and 21 for sector protection waveforms and algorithms. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. otherwise the device will read 00h for an unprotected sector. in this mode, the lower order address, except for a 0 , a 1 and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to v il in word mode. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order address pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) represents the sector address will produce a logical 1 at dq 0 for a protected sector. see tables 5.1 to 5.4 for autoselect codes. temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the device in order to change data. the sector unprotection mode is activated by the command register. in this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the mode is taken away using the command register, all previously protected sectors will be protected again. (see figure 22.)
mbm29pl3200te/be 70/90 21 boot block sector protection the write protection function provides a hardware method of protecting certain outermost 16 k word ( 16 mode) sector without using v id . if the system asserts v il on the wp pin, the device disables program and erase functions in the outermost 16 k word sector independently of whether this sector was protected or unprotected using the method described in sector protection/unprotection. the outermost 16 k word sector is the highest addresses in mbm29pl3200te, or the lowest addresses in mbm29pl3200be. (mbm29pl3200te : sa18, mbm29pl3200be : sa0) if the system asserts v il on the wp pin, the device reverts to whether the outermost 16 k word sector was last set to be protected or unprotected. that is, sector protection or unprotection for this sector depends on whether this was last protected or unprotected using the method described in sector protection/unprotection. accelerated program operation the device offers accelerated program operation which enables high-speed programming. if the system asserts v acc to the acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60 % . this function is primarily intended to allow high-speed programming, so caution is needed as the sector group will temporarily be unprotected. the system would use a fast program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device is automatically set to fast mode. therefore, the present sequence could be used for programming and detection of completion in acceleration mode. removing v acc from the acc pin returns the device to normal operation. do not remove v acc from the acc pin while programming. see figure 16.
mbm29pl3200te/be 70/90 22 n n n n command definitions the device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in an improper sequence will reset the device to the read mode. table 4 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 15 to dq 0 and dq 31 to dq 16 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. micro- processor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read character- istics and waveforms for specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, both manufacture and device codes must be accessible while the device resides in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. fol- lowing the last command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle at address xx01h (xx02h for 8) returns 7eh indicating that this device uses an extended device code. the successive read cycle from xx0eh to xx0fh returns this extended device code for this device. (see tables 5.1 to 5.4.) the sector state (protection or unprotection) will be indicated by address xx02h for 32 (xx04h for 16). scanning the sector addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should perform margin mode verification on the protected sector. (see tables 2 and 3.) to terminate the operation, it is necessary to write the read/reset command sequence into the register and to write the autoselect command during the operation by executing it after writing the read/reset command sequence. word/double word programming the device is programmed on a word-by-word (or double word-by-double word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later, and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of the last ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. (see figures 6 and 7.) the system can determine the status of the program operation by using dq 7 (data polling), or dq 6 (toggle bit). the data polling and toggle bit must be performed at the memory location which is being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit. then, the device return to the read mode and addresses are no longer latched. (see table 10, hardware sequence flags.) therefore, the device requires that a valid address be supplied by the system at this time. hence, data polling must be performed at the memory location which is being programmed.
mbm29pl3200te/be 70/90 23 any commands written to the chip during this period will be ignored. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. figure 17 illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six-bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence, the device will automatically program and verify the entire memory for an all- zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), or dq 6 (toggle bit). the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section), at which time the device returns to the read mode. chip erase time = sector erase time all sectors + chip program time (preprogramming) figure 18 illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we , whichever happens later, while the command (data = 30h) is latched on the rising edge of ce or we , which happens first. after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on table 4. this sequence is followed with writes of the sector erase command (30h) to addresses in other sectors desired to be concurrently erased. the time between writes must be less than t tow , or that command will not be accepted and erasure will not start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we , whichever happens first, will initiate the execution of the sector erase command (s). if another falling edge of ce or we , whichever happens first, occurs within the t tow time-out window, the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open; see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. in that case, restart the erase on those sectors and allow them to complete. (refer to write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 19). sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector (s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors, the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling) or dq 6 (toggle bit). the sector erase begins after the t tow time out from the rising edge of ce or we , whichever happens first ,for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section), at which time the device returns to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time = [sector erase time + sector program time (preprogramming)] number of sector erase.
mbm29pl3200te/be 70/90 24 erase suspend/resume the erase suspend/resume command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. erase suspend command is applicable only during the sector erase operation, which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of t spd to suspend the erase operation. when the device has entered the erase-suspended mode, the dq 7 bit will be at logic 1 and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode will become the erase-suspend-program mode. again, pro- gramming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase-suspended program operation is detected by the data polling of dq 7 or by the toggle bit i (dq 6 ), which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing.
mbm29pl3200te/be 70/90 25 extended command (1) fast mode the device has a fast mode function. this mode dispenses with the initial two unlock cycles required in the standard program command sequence by writing a fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write a fast mode reset command into the command register. (refer to figure 23.) the v cc active current is required even if ce = v ih during fast mode. (2) fast programming in fast mode, the programming can be executed with two bus cycle operation. the embedded program algorithm is executed by writing a program set-up command (a0h) and data write cycles (pa/pd). (refer to figure 23.) (3) cfi (common flash memory interface) the cfi (common flash memory interface) specification outlines the device and host system software interro- gation handshake which allows specific vendor-specified software algorithms to be used for entire families of the device. this allows device-independent, jedec id-independent, and forward-and backward-compatible software support for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. following the command write, a read cycle from specific address retrieves device information. please note that output data of upper byte (dq 15 to dq 8 ) is 0 in word mode (16 bit) read. refer to the cfi code table. to terminate operation, it is necessary to write the read/reset command sequence into the register.
mbm29pl3200te/be 70/90 26 hidden rom (hi-rom) region the hi-rom feature provides a flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hi-rom region is protected, any further modifi- cation of that region is impossible. this ensures the security of the esn once the product is shipped to the field. the hi-rom region is 512 words in length. after the system has written the enter hi-rom command sequence, it may read the hidden rom region by using device addresses a 7 to a 0 (a 11 to a 8 are 00, a 19 to a 12 are dont care). that is, the device sends only program command that would normally be sent to the address to the hi- rom region. this mode of operation continues until the system issues the exit hi-rom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the address. hidden rom (hi-rom) entry command the device has a hidden rom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. program/erase is possible in this area until it is protected. however, once it is protected, it is impossible to unprotect, so please use this with caution. hidden rom area is 512 words. this area is normally the outermost 16 k word boot block area. therefore, write the hidden rom entry command sequence to enter the hidden rom area. it is called hidden rom mode when the hidden rom area appears. hidden rom (hi-rom) program command to program the data to the hidden rom area, write the hidden rom program command sequence during hidden rom mode. this command is the same as the program command in usual except to write the command during hidden rom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data polling, and dq 6 toggle bit. need to pay attention to the address to be programmed. if the address other than the hidden rom area is selected to program, data of the address will be changed. hidden rom (hi-rom) protect command the method to protect the hidden rom is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hidden rom area and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0), and apply the write pulse during the hidden rom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) and the sector address in the hidden rom area, and read. when 1 appears on dq 0 , the protect setting is completed. 0 will appear on dq 0 if it is not protected. please apply write pulse agian. the same command sequence could be used for the above method because other than the hidden rom mode, it is the same as the sector protect in the past. please refer to function explanation secor protection for details of the sector protect setting. other sector will be effected if the address other than those for hidden rom area is selected for the sector address, so please be carefull. once it is protected, protection can not be cancelled, so please pay the closest attention.
mbm29pl3200te/be 70/90 27 write operation status detailed in table 10 are all the status flags that can be used to check the status of the device for current mode operation. during sector erase, the part provides the status flags automatically to the i/o ports. the information on dq 2 is address sensitive. this means that if an address from an erasing sector is consecutively read, then the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non-erasing sector is consecutively read. this allows users to determine which sectors are in erase and which are not. once erase suspend is entered, address sensitivity still applies. if the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. if the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits. table 10 hardware sequence flags *: successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. notes : 1.dq 0 and dq 1 are reserve pins for future use. 2.dq 4 is fujitsu internal use only. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle * erase suspended mode erase suspend read (erase suspended sector) 1100t oggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1 * exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29pl3200te/be 70/90 28 dq 7 data polling the device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the device will produce a complement of data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 on dq 7 . the flowchart for data polling (dq 7 ) is shown in figure 19. for programming, the data polling is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at the sector address of sectors being erased, not protected sectors. otherwise, the status may be invalid. once the embedded algorithm operation is close to being completed, the device data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has valid data, data outputs on dq 6 to dq 0 may be still invalid. the valid data on dq 7 to dq 0 will be read on successive read attempts. the data polling feature is active only during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see table 10.) see figure 9 for the data polling timing specifications and diagrams. dq 6 toggle bit i the device also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during the embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written is protected, the toggle bit will toggle for about 1 m s and then stop toggling with data unchanged. in erase, device will erase all selected sectors except for ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 m s and then drop back into read mode, having data unchanged. either ce or oe toggling will cause dq 6 to toggle. in addition, an erase suspend/resume command will cause dq 6 to toggle. see figure 10 and figure 20 for the toggle bit i timing specifications and diagrams.
mbm29pl3200te/be 70/90 29 dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is only operating function of device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in tables 2 and 3. the dq 5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads valid data on dq 7 bit and dq 6 never stops toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device with the command sequence. dq 3 sector erase timer after completion of the initial sector erase command sequence, sector erase time-out will begin. dq 3 will remain low until the time-out is completed. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates that the device has been written with a valid erase command, dq 3 may be used to determine whether the sector erase timer window is still open. if dq 3 is high (1), the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 is high on the second status check, the command may not have been accepted. see table 10 : hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows : for example, dq 2 and dq 6 can be used together to determine whether the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also table 11 and figure 11. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector.
mbm29pl3200te/be 70/90 30 reading toggle bits dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ). if it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (refer to figure 20.) table 11 toggle bit status note : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non- erase suspend sector address will indicate logic 1 at the dq 2 bit. double word/word configuration dw/w pin selects double word (32-bit) mode or word (16-bit) mode for the device. when this pin is driven high, the device operates in the double word (32-bit) mode. data is read and programmed at dq 31 to dq 0 . when this pin is driven low, the device operates in word (16-bit) mode. in this mode, the dq 31 /a -1 pin becomes the lowest address bit, and dq 30 to dq 16 bits are tri-stated. however, the command bus cycle is always an 16-bit operation and hence commands are written at dq 31 to dq 16 and dq 15 to dq 0 bits are ignored. refer to figures 12, 13 and 14 for the timing diagram. data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power-up, the device automatically resets the internal state machine to read mode. also, with its control register architecture, alteration of memory contents only occurs after successful completion of the specific multi-bus cycle command sequence. the device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle (note) erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1 (note)
mbm29pl3200te/be 70/90 31 low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko (min.). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko (min.). if the embedded erase algorithm is interrupted, there is possibility that the erasing sector (s) can not be used. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle, ce and we must be l while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to read mode on power-up.
mbm29pl3200te/be 70/90 32 n n n n absolute maximum ratings *1: minimum dc voltage on input or l/o pins is - 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input or l/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods of up to 20 ns. *2: minimum dc input voltage on a 9 , oe and acc pins is - 0.5 v. during voltage transitions, a 9 , oe and acc pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed 9.0 v. maximum dc input voltage on a 9 , oe and acc pins is + 13.0 v which may overshoot to 14.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions operating ranges define those limits between which the functionality of the device is quaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. storage temperature tstg - 55 + 125 c ambient temperature with power applied ta - 40 + 85 c voltage with respect to ground all pins except a 9 , oe , and acc * 1 v in , v out - 0.5 v cc + 0.5 v power supply voltage * 1 v cc - 0.5 + 4.0 v a 9 , oe , and acc * 2 v in - 0.5 + 13.0 v parameter symbol part no. value unit min. max. ambient temperature ta mbm29pl3200te/be 70 - 20 + 70 c mbm29pl3200te/be 90 - 40 + 85 power supply voltage v cc mbm29pl3200te/be 70 + 3.0 + 3.6 v mbm29pl3200te/be 90 + 2.7 + 3.6
mbm29pl3200te/be 70/90 33 n n n n maximum overshoot/undershoot + 0.6 v - 0.5 v 20 ns - 2.0 v 20 ns 20 ns figure 1 maximum undershoot waveform v cc + 0.5 v v cc + 2.0 v + 2.0 v 20 ns 20 ns 20 ns figure 2 maximum overshoot waveform 1 + 13.0 v v cc + 0.5 v + 14.0 v 20 ns 20 ns 20 ns note : this waveform is applied for a 9 , oe and acc. figure 3 maximum overshoot waveform 2
mbm29pl3200te/be 70/90 34 n n n n electrical characteristics 1. dc characteristics *1: the l cc current listed includes both the dc operating current and the frequency dependent component. *2: l cc active while embedded erase or embedded program is in progress. *3: automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: (v id - v cc ) do not exceed 9 v. parameter symbol conditions value unit min. max. input leakage current (except wp , acc) i li v in = v ss to v cc , v cc = v cc max. - 1.0 + 1.0 m a output leakage current (except wp , acc) i lo v out = v ss to v cc , v cc = v cc max. - 1.0 + 1.0 m a input leakage current (wp , acc) i li v in = v ss to v cc , v cc = v cc max. - 2.0 + 2.0 m a output leakage current (wp , acc) i lo v out = v ss to v cc , v cc = v cc max. - 2.0 + 2.0 m a a 9 , oe , acc inputs leakage current i lit v cc = v cc max., a 9 , oe , acc = 12.5 v ? 35 m a v cc active current (read) * 1 i cc1 ce = v il , oe = v ih f = 10 mhz word ? 80 ma double word 80 ce = v il , oe = v ih f = 5 mhz word ? 50 ma double word 50 v cc active current (program/erase) * 2 i cc2 ce = v il , oe = v ih ? 80 ma v cc current (standby) i cc3 v cc = v cc max., ce = v cc 0.3 v ? 5 m a v cc current (automatic sleep mode) * 3 i cc4 v cc = v cc max., ce = v ss 0.3 v, v in = v cc 0.3 v or v ss 0.3 v ? 5 m a v cc active current (page read mode) i cc5 ce = v il , oe = v ih 30 mhz ? 12 ma 40 mhz ? 15 acc accelerated program current i acc v cc = v cc max., acc = v acc max. ? 20 ma input low level v il ?- 0.5 0.8 v input high level v ih ? 2.0 v cc + 0.3 v voltage for program acceleration * 4 v acc ? 11.5 12.5 v voltage for autoselect and sector protection (a 9 , oe ) * 4 v id ? 11.5 12.5 v output low voltage level v ol i ol = 4.0 ma, v cc = v cc min. ? 0.45 v output high voltage level v oh1 i oh = - 2.0 ma, v cc = v cc min. 2.4 ? v v oh2 i oh = - 100 m av cc - 0.4 ? v low v cc lock-out voltage v lko ? 2.3 2.5 v
mbm29pl3200te/be 70/90 35 2. ac characteristics (1) read only operations characteristics parameter symbol condition value unit 70 * 1 90 * 2 jedec standard min. max. min. max. read cycle time t avav t rc ? 70 ? 90 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 70 ? 90 ns page read cycle time ? t prc ? 25 35 ns page address to output delay ? t pacc ce = v il oe = v il ? 25 ? 35 ns chip enable to output delay t elqv t ce oe = v il ? 70 ? 90 ns output enable to output delay t glqv t oe ?? 25 ? 35 ns chip enable to output high-z t ehqz t df ?? 25 ? 30 ns output enable to output high-z t ghqz t df ?? 25 ? 30 ns output hold time from address, ce or oe , whichever occurs first t axqx t oh ? 4 ? 5 ? ns ce or dw/w switching low or high ? t elfl t elfh ?? 5 ? 5ns *1: test conditions : output load : 1 ttl gate and 50 pf input rise and fall times : 5 ns input pulse levels : 0.0 v to 3.0 v timing measurement reference level input : 1.5 v output : 1.5 v *2 test conditions : output load : 1 ttl gate and 100 pf input rise and fall times : 5 ns input pulse levels : 0.0 v to 3.0 v timing measurement reference level input : 1.5 v output : 1.5 v c l 3.3 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w figure 4 test conditions
mbm29pl3200te/be 70/90 36 (2) write (erase/program) operations symbol parameter value unit 70 * 1 90 * 2 jedec standard min. typ. max. min. typ. max. t avav t wc write cycle time 70 ?? 90 ?? ns t avwl t as address setup time 0 ?? 0 ?? ns t wlax t ah address hold time 45 ?? 45 ?? ns t dvwh t ds data setup time 35 ?? 45 ?? ns t whdx t dh data hold time 0 ?? 0 ?? ns ? t oes output enable setup time 0 ?? 0 ?? ns ? t oeh output enable hold time read 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? ns t ghwl t ghwl read recover time before write 0 ?? 0 ?? ns t ghel t ghel read recover time before write (oe high to ce low) 0 ?? 0 ?? ns t elwl t cs ce setup time 0 ?? 0 ?? ns t wlel t ws we setup time 0 ?? 0 ?? ns t wheh t ch ce hold time 0 ?? 0 ?? ns t ehwh t wh we hold time 0 ?? 0 ?? ns t wlwh t wp write pulse width 35 ?? 35 ?? ns t eleh t cp ce pulse width 35 ?? 35 ?? ns t whwl t wph write pulse width high level 30 ?? 30 ?? ns t ehel t cph ce pulse width high level 30 ?? 30 ?? ns t whwh1 t whwh1 programming operation double word ? 18.3 ?? 18.3 ? m s word ? 14.3 ?? 14.3 ? t whwh2 t whwh2 sector erase operation * 3 ? 4 ?? 4 ? s ? t vcs v cc setup time 50 ?? 50 ?? m s ? t vidr rise time to v id * 4 500 ?? 500 ?? ns ? t vaccr rise time to v acc * 5 500 ?? 500 ?? ns ? t vlht voltage transition time * 4 4 ?? 4 ?? m s ? t wpp write pulse width * 4 100 ?? 100 ?? m s ? t oesp oe setup time to we active * 4 4 ?? 4 ?? m s ? t csp ce setup time to we active * 4 4 ?? 4 ?? m s ? t eoe delay time from embedded output enable ?? 70 ?? 90 ns ? t flqz dw/w switching low to output high-z ?? 30 ?? 30 ns ? t fhqv dw/w switching high to output active 35 ?? 30 ?? ns ? t tow erase time-out time 50 ?? 50 ?? m s ? t spd erase suspend transition time ?? 20 ?? 20 m s
mbm29pl3200te/be 70/90 37 *3: this does not include the preprogramming time. *4: this timing is for sector protection operation. *5: this timing is for accelerated program operation. *1: test conditions : output load : 1 ttl gate and 50 pf input rise and fall times : 5 ns input pulse levels : 0.0 v to 3.0 v timing measurement reference level input : 1.5 v output : 1.5 v *2 test conditions : output load : 1 ttl gate and 100 pf input rise and fall times : 5 ns input pulse levels : 0.0 v to 3.0 v timing measurement reference level input : 1.5 v output : 1.5 v
mbm29pl3200te/be 70/90 38 n n n n erase and programming performance n n n n pin capacitance note : test conditions ta = 25 c, f = 1.0 mhz n n n n fbga pin capacitance note : test conditions ta = 25 c, f = 1.0 mhz parameter value unit comments min. typ. max. sector erase time ? 440s excludes programming time prior to erasure word programming time ? 14.3 360 m s excludes system-level overhead double word programming time ? 18.3 480 chip programming time ? 20 280 s excludes system-level overhead erase/program cycle 100,000 ?? cycle ? parameter symbol condition value unit typ. max. input capacitance c in v in = 067.5pf output capacitance c out v out = 0 8 10.0 pf control pin capacitance c in2 v in = 0 8 10.0 pf parameter symbol condition value unit typ. max. input capacitance c in v in = 0tbdtbdpf output capacitance c out v out = 0tbdtbdpf control pin capacitance c in2 v in = 0tbdtbdpf
mbm29pl3200te/be 70/90 39 n n n n switching waveforms ? key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h "h" or "l": any change permitted does not apply will be steady will be change from h to l will be change from l to h changing, state unknown center line is high- impedance "off" state address address stable high-z high-z ce oe we outputs output valid t rc t acc t oe t df t ce t oh t oeh figure 5.1 read operation timing diagram
mbm29pl3200te/be 70/90 40 output a 1 to a 0 (a -1 ) a 19 to a 2 ce oe we aa ab ac t rc t acc t ce t oe t oh t oh t oh t df t pacc t pacc t oeh t prc da db dc same page address high-z figure 5.2 page read operation timing diagram
mbm29pl3200te/be 70/90 41 address data ce oe we 3rd bus cycle data polling 555h pa a0h pd dq 7 d out d out pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t ds t dh t df t oh t oe t cs t ch notes : 1.pa is address of the memory location to be programmed. 2.pd is data to be programmed at word address. 3.dq 7 is the output of the complement of the data written to the device. 4.d out is the output of the data written to the device. 5.figure indicates last two bus cycles out of four bus cycle sequence. 6.these waveforms are for the 32 mode. (the addresses differ from 16 mode.) figure 6 alternate we controlled program operation timing diagram
mbm29pl3200te/be 70/90 42 address data we oe ce 3rd bus cycle data polling 555h pa a0h pd dq 7 d out pa t wc t as t ah t whwh1 t cph t cp t ghel t ds t dh t ws t wh figure 7 alternate ce controlled program operation timing diagram notes : 1.pa is address of the memory location to be programmed. 2.pd is data to be programmed at word address. 3.dq 7 is the output of the complement of the data written to the device. 4.d out is the output of the data written to the device. 5.figure indicates last two bus cycles out of four bus cycle sequence. 6.these waveforms are for the 32 mode. (the addresses differ from 16 mode.)
mbm29pl3200te/be 70/90 43 address data v cc ce oe we 555h 2aah 555h 555h 2aah sa* t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h 30h for sector erase figure 8 chip/sector erase operation timing diagram note : 1.sa is the sector address for sector erase. addresses = 555h (double word), aaah (word) for chip erase. 2.these waveforms are for the 32 mode. (the addresses differ from 16 mode.)
mbm29pl3200te/be 70/90 44 t oeh t ch t oe t ce t df t eoe t whwh1 or 2 ce dq 7 dq 6 to dq 0 dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we high-z high-z data data * figure 9 data polling during embedded algorithm operation timing diagram * : dq 7 = valid data (the device has completed the embedded operation)
mbm29pl3200te/be 70/90 45 t oeh ce we t oes oe dq 6 t oe t dh data (dq 0 to dq 7 ) dq 6 = toggle dq 6 = stop toggling dq 6 = toggle dq 0 to dq 7 data valid * figure 10 toggle bit i during embedded algorithm operation timing diagram * : dq 6 = stops toggling. (the device has completed the embedded operation.) enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 we toggle dq 2 and dq 6 with oe figure 11 dq 2 vs. dq 6 note : dq 2 is read from the erase-suspended sector.
mbm29pl3200te/be 70/90 46 t ce t fhqv t elfh a -1 data output (dq 15 to dq 0 ) data output (dq 30 to dq 0 ) dq 31 ce dw/w dq 30 to dq 0 dq 31 /a -1 figure 12 double word mode configuration timing diagram t elfl t acc t flqz a -1 data output (dq 30 to dq 0 ) data output (dq 15 to dq 0 ) dq 31 ce dw/w dq 30 to dq 0 dq 31 /a -1 figure 13 word mode configuration timing diagram t as t ah ce or we dw/w input valid the falling edge of the last write signal figure 14 dw/w timing diagram for write operations
mbm29pl3200te/be 70/90 47 t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht a 19 , a 18 , a 17 a 16 , a 15 , a 14 a 13 , a 12 a 0 a 1 a 6 a 9 v cc oe v id 3 v v id 3 v we ce data sax 01h say figure 15 sector protection timing diagram sax : sector address for initial sector say : sector address for next sector note : a -1 is v il on word mode.
mbm29pl3200te/be 70/90 48 acceleration period t vlht t vlht t vcs t vlht t vaccr program or erase command sequence v cc v acc v ih we ce acc figure 16 accelerated program timing diagram
mbm29pl3200te/be 70/90 49 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify byte ? data polling device program command sequence* (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in progress figure 17 embedded program tm algorithm * : the sequence is applied for 32 mode. the addresses differ from 16 mode. embedded algorithm
mbm29pl3200te/be 70/90 50 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling or toggle bit from device write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence* (address/command) : individual sector/multiple sector* erase command sequence (address/command) : additional sector erase commands are optional. figure 18 embedded erase tm algorithm * : the sequence is applied for 32 mode. the addresses differ from 16 mode. embedded algorithm
mbm29pl3200te/be 70/90 51 dq 7 = data? dq 5 = 1? fail pass dq 7 = data? * read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va start no no no yes yes yes figure 19 data polling algorithm * : dq 7 should be rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation.
mbm29pl3200te/be 70/90 52 toggle bit = toggle? dq 5 = 1? toggle bit = toggle? read (dq 7 to dq 0 ) addr. = "h" or "l" read (dq 7 to dq 0 ) addr. = "h" or "l" read (dq 7 to dq 0 ) twice addr. = "h" or "l" start no no no yes yes yes program/erase operation not complete.write reset command program/erase operation complete (note 1) (notes 1 , 2) figure 20 toggle bit algorithm notes : 1.read toggle bit twice to determine whether or not it is toggling. 2.recheck toggle bit because it may stop toggling as dq 5 changes to 1.
mbm29pl3200te/be 70/90 53 start no no no yes yes yes data = 01h? device failed plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector protection completed protect another sector ? increment plscnt read from sector addr. = sa, a 1 = v ih a 6 = a 3 = a 2 = a 0 = v il setup sector group addr. a 19 , a 18 , a 17 ,a 16 , a 15 , a 14 , a 13 , a 12 oe = v id , a 9 = v id , ce = v il , a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih activate we pulse time out 100 m s we = v ih , ce = oe = v il (a 9 should remain v id ) () () * figure 21 sector protection algorithm * : a -1 is v il on word mode.
mbm29pl3200te/be 70/90 54 start perform erase or program operations temporary unprotect enable command write (note 1) temporary unprotect disable command write temporary sector unprotection completed (note 2) figure 22 temporary sector unprotection algorithm notes : 1.all protected sectors are unprotected. 2.all previously protected sectors are protected once again.
mbm29pl3200te/be 70/90 55 555h/aah 555h/20h xxxxh/90h xxxxh/f0h xxxh/a0h 2aah/55h program address/program data programming completed last address? increment address verify data? data polling device start no no yes yes set fast mode in fast program reset fast mode figure 23 embedded programming algorithm for fast mode notes 1 : the sequence is applied for 32 mode. 2 : the addresses differ from 16 mode. fast mode algorithm
mbm29pl3200te/be 70/90 56 n n n n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm29pl3200 t e 70 pfv device number/description mbm29pl3200 32 mega-bit (2 m 16-bit or 1 m 32-bit) cmos page mode flash memory 3.0 v-only read, write, and erase package type pfv = 90-pin shrink outline l-leaded package (ssop) pbt = 84-ball fine pitch ball grid array package (fbga) speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector valid combinations mbm29pl3200te/be 70 90 pfv pbt valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.
mbm29pl3200te/be 70/90 57 n n n n package dimensions (continued) 90-pin plastic ssop (fpt-90p-m01) dimensions in mm (inches) c 2000 fujitsu limited f90001s-1c-1 1 45 46 90 23.70?.30(.933?012) 0.50(.020) 0.22?.05 (.009?002) m 0.08(.003) 0.08(.003) 13.30?.20 (.524?008) 16.00?.30 (.630?012) .007 ?001 +.002 ?.03 +0.05 0.17 0.55?.10 (.022?004) 1.80?.10 (.071?004) (mounting height) (stand off) "a" 0.25(.010) 0.73/1.00 (.029/.039) 0?8 details of "a" part index
mbm29pl3200te/be 70/90 58 (continued) 84-ball plastic fbga (bga-84p-m01) dimensions in mm (inches) c 2000 fujitsu limited b84001s-1c-1 11.00?.10(.433?004) 8.00?.10 (.315?004) index-mark area 0.10(.004) 0.38?.10 (.015?004) (stand off) .041 ?004 +.006 ?.10 +0.15 1.05 (mounting height) 0.80(.031) typ 7.20(.283)ref 6.40(.252) ref a b c d e f g h j k 9 8 7 6 5 4 3 2 1 index side 84-0.45?.05 (84-.018.002) m 0.08(.003)
mbm29pl3200te/be 70/90 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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